IPVLPIOTRAES30

• The IPVLPIOTRAES30 soft IP is intended to be used in Xilinx FPGA kits as an RTL optimized code. In addition, it is available as a hard ASIC IP which can be cost-effectively ported across process nodes and technology foundries.

• The hard ASIC IP provides up to 30Mbps throughput with  power consumption of 0.2mW and very small Silicon area.

To purchase or request a quotation, email: sales@ipvalleyinc.com